
module clk100K(
		     input  clk50M,
		     input  rst_n,
		     output clk100k
			  );
			  
  reg [31:0] div_cnt;
  reg        clk100k_r;
  
  assign clk100k =clk100k_r;
  
  always@(posedge clk50M or negedge rst_n)
  begin
      if(!rst_n)
	       begin
	         div_cnt   <= 0;
	         clk100k_r <= 1'b0;
	       end
      else
	       begin
	         if(div_cnt >= 250)
	             begin
		            div_cnt <= 0;
		            clk100k_r <= ~clk100k_r;
		          end
            else
	             begin
		            div_cnt <= div_cnt+1;
		          end
	       end
  end
endmodule 